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d a t a sh eet preliminary speci?cation file under integrated circuits, ic02 1998 jul 23 integrated circuits saa4977h besic
1998 jul 23 2 philips semiconductors preliminary speci?cation besic saa4977h contents 1 features 2 general description 3 quick reference data 4 ordering information 5 block diagram 6 pinning information 6.1 pinning 6.2 pin description 7 functional description 7.1 analog-to-digital conversion 7.2 digital processing at 1f h level 7.3 digital processing at 2f h level 7.4 digital-to-analog conversion 7.5 microprocessor 7.6 memory controller 7.7 line locked clock generation 7.8 clock and sync interfacing 7.9 4:1:1 i/o interfacing 7.10 test mode operation 7.11 i 2 c-bus control registers 8 limiting values 9 thermal characteristics 10 characteristics 11 application 12 package outline 13 soldering 13.1 introduction 13.2 reflow soldering 13.3 wave soldering 13.4 repairing soldered joints 14 definitions 15 life support applications 16 purchase of philips i 2 c components
1998 jul 23 3 philips semiconductors preliminary speci?cation besic saa4977h 1 features internal prefilter clamp circuit analog agc line locked pll triple yuv 8-bit analog-to-digital converter (adc) horizontal compression field rate up-conversion (50 to 100 hz or 60 to 120 hz) 4:1:1 digital i/o interface digital cti (dcti) digital luminance peaking triple 10-bit digital-to-analog converter (dac) memory controller embedded microprocessor 16 kbyte rom 256 byte ram i 2 c-bus interface synchronous no parity eight bit reception and transmission (snert) interface. 2 general description the saa4977h is a video processing ic providing analog yuv interfacing, video enhancing features, memory controlling and an embedded 80c51 microprocessor core. it is applicable especially for field rate up-conversion (50 to 100 hz or 60 to 120 hz) in cooperation with a 2.9 mbit field memory. it is designed for applications together with: saa4955/56tj, tms4c2972/73 (serial field memories) saa4990h (prozonic) saa4991wp (melzonic). 3 quick reference data 4 ordering information symbol parameter min. typ. max. unit v dda(1,2,3) analog supply voltage front-end 4.75 5.0 5.25 v v ddd(1,2,3) digital supply voltage front-end 4.75 5.0 5.25 v v dda(4,5) analog supply voltage back-end 3.15 3.3 3.45 v v ddd(4,5,6) digital supply voltage back-end 3.15 3.3 3.45 v v ddio i/o supply voltage back-end 4.75 5.0 5.25 v i dda(1,2,3) analog supply current front-end - 85 100 ma i ddd(1,2,3) digital supply current front-end - 65 80 ma i dda(4,5) analog supply current back-end - 25 35 ma i ddd(4,5,6) digital supply current back-end - 40 55 ma i ddio i/o supply current back-end - 110ma p tot total power dissipation -- 1.3 w t amb operating ambient temperature - 20 - +60 c type number package name description version saa4977h qfp80 plastic quad ?at package; 80 leads (lead length 1.95 mm); body 14 20 2.8 mm sot318-2
1998 jul 23 4 philips semiconductors preliminary speci?cation besic saa4977h this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... 5 block diagram fig.1 block diagram. u ll pagewidth mgm592 clamp agc analog prefilter triple adc 8 bit variable y-delay uv clamp correction down sampling 4 : 4 : 4 to 4 : 1 : 1 horizontal compression formatter saa4977h variable y-delay reformatter up sampling 4 : 1 : 1 to 4 : 2 : 2 y-peaking dcti up sampling 4 : 2 : 2 to 4 : 4 : 4 blanking side- panels triple dac 10 bit ram microprocessor i 2 c- bus snert- bus i/o port rom 26 28 yin uin vin 30 yout 79 uout 76 vout 74 37 to 34 59 to 62 51 to 58 45 to 38 yi7 to yi0 yo7 to yo0 uvi7 to uvi4 uvo7 to uvo4 8 4 4 8 control interface memory control (display) 3 to 7 5 12, 13, 10 3 1, 2 2 p1.5 to p1.1 snda, sncl, snrst 68 9 hrd 71, 72 2 hdfl vdfl 66 blnd 63, 64 2 re ie2 70 lld control interface memory control (acquisition) 24 rstw 32 we 20 va acquisition pll 47 swc 33 lla 22 ha 17 selclk test control block 15 tms 49 trst sda, scl rst
1998 jul 23 5 philips semiconductors preliminary speci?cation besic saa4977h 6 pinning information 6.1 pinning fig.2 pin configuration. handbook, full pagewidth saa4977h mgm593 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 64 63 62 61 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 uvi6 uvi7 yi0 yi1 yi2 ie2 re uvi4 uvi5 yi3 yi4 yi5 yi6 yi7 v ssd3 trst v ssd2 swc v ddd3 yo7 yo6 yo5 yo4 yo3 p1.3 p1.2 p1.1 v ddd5 rst sda scl p1.5 p1.4 snrst v ddd6 snda sncl v ssd4 tms v ssd1 selclk v ddd1 v ddd2 va v ssa1 ha v dda1 rstw 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 v dda2 yin v ssa2 uin v dda3 vin v ssa3 we lla uvo4 uvo5 uvo6 uvo7 yo0 yo1 yo2 v dda5 yout v ssa6 v ssa5 uout v dda4 vout v ssa4 vdfl hdfl lld v ddd4 hrd v ddio blnd v ssio 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
1998 jul 23 6 philips semiconductors preliminary speci?cation besic saa4977h 6.2 pin description table 1 qfp80 package symbol pin description sda 1 i 2 c-bus serial data (p1.7) scl 2 i 2 c-bus serial clock (p1.6) p1.5 3 port 1 data input/output signal 5 p1.4 4 port 1 data input/output signal 4 p1.3 5 port 1 data input/output signal 3 p1.2 6 port 1 data input/output signal 2 p1.1 7 port 1 data input/output signal 1 v ddd5 8 digital supply voltage 5 (3.3 v) rst 9 microprocessor reset input snrst 10 snert restart (port 1.0) v ddd6 11 digital supply voltage 6 (3.3 v) snda 12 snert data sncl 13 snert clock v ssd4 14 digital ground 4 tms 15 test mode select v ssd1 16 digital ground 1 selclk 17 select acquisition clock input; internal pll if high, external clock if low v ddd1 18 digital supply voltage 1 (5 v) v ddd2 19 digital supply voltage 2 (5 v) va 20 vertical synchronization input, acquisition part v ssa1 21 analog ground 1 ha 22 analog/digital horizontal reference input v dda1 23 analog supply voltage 1 (5 v) rstw 24 reset write signal output, memory 1 v dda2 25 analog supply voltage 2 (5 v) yin 26 y analog input v ssa2 27 analog ground 2 uin 28 u analog input v dda3 29 analog supply voltage 3 (5 v) vin 30 v analog input v ssa3 31 analog ground 3 we 32 write enable signal output, memory 1 lla 33 acquisition clock input uvo4 34 v digital output bit 0 uvo5 35 v digital output bit 1 uvo6 36 u digital output bit 0 uvo7 37 u digital output bit 1 yo0 38 y digital output bit 0
1998 jul 23 7 philips semiconductors preliminary speci?cation besic saa4977h yo1 39 y digital output bit 1 yo2 40 y digital output bit 2 yo3 41 y digital output bit 3 yo4 42 y digital output bit 4 yo5 43 y digital output bit 5 yo6 44 y digital output bit 6 yo7 45 y digital output bit 7 (msb) v ddd3 46 digital supply voltage 3 (5 v) swc 47 serial write clock output v ssd2 48 digital ground 2 trst 49 test reset, active low v ssd3 50 digital ground 3 yi7 51 y digital input bit 7 (msb) yi6 52 y digital input bit 6 yi5 53 y digital input bit 5 yi4 54 y digital input bit 4 yi3 55 y digital input bit 3 yi2 56 y digital input bit 2 yi1 57 y digital input bit 1 yi0 58 y digital input bit 0 uvi7 59 u digital input bit 1 uvi6 60 u digital input bit 0 uvi5 61 v digital input bit 1 uvi4 62 v digital input bit 0 re 63 read enable signal output, memory 1 ie2 64 input enable signal output, memory 2 v ssio 65 i/o ground blnd 66 horizontal blanking signal output, display part v ddio 67 i/o supply voltage (5 v) hrd 68 horizontal reference signal output, de?ection part v ddd4 69 digital supply voltage 4 (3.3 v) lld 70 display clock input hdfl 71 horizontal synchronization signal output, de?ection part vdfl 72 vertical synchronization signal output, de?ection part v ssa4 73 analog ground 4 vout 74 v analog output v dda4 75 analog supply voltage 4 (3.3 v) uout 76 u analog output v ssa5 77 analog ground 5 symbol pin description
1998 jul 23 8 philips semiconductors preliminary speci?cation besic saa4977h v ssa6 78 analog ground 6 yout 79 y analog output v dda5 80 analog supply voltage 5 (3.3 v) symbol pin description 7 functional description 7.1 analog-to-digital conversion 7.1.1 c lamp circuit , clamping y to digital level 16 and uv to 0 (2 s complement ) a clamp circuit is applied for each input channel, to map the colourless black level in each video line (on the sync back porch) to level 16 for y and to the centre level of the converters for u and v. during the clamp period, an internally generated clamp pulse is used to switch on the clamp action. an operational transconductance amplifier like construction, which references to voltage reference points in the ladders of the adcs, will provide a current on the input of the yuv signals, in order to bring the signals to the correct dc value. this current is proportional to the dc error, but is limited to 100 m a. when the clamping action is off, the residual clamp current should be very low in order not to drift away within a video line. 7.1.2 g ain elements for automatic gain control a variable amplifier is used to map the possible yuv input range to the adc range. a rise of 6 db up to a drop fall of 6 db w.r.t. the nominal values can be achieved. the gain setting within this range is done digitally via control registers. for this purpose a gain setting dac is incorporated. the smallest step in the gain setting should be hardly visible on the picture, which can be met with smallest steps of 0.4%/step. luminance and chrominance gain settings can be separately controlled. the reason for this split is that u and v may be gain adjusted already, whereas luminance is to be adjusted by the saa4977h agc. on the other hand, for rgb originated sources, y, u and v should be adjusted with the same agc gain. 7.1.3 a nalog anti - aliasing prefiltering a third order linear phase filter is applied on each of the y, u and v channels. it provides a notch on f clk (16 mhz) to strongly prevent aliasing to low frequencies, which would be the most disturbing. the bandwidth of the filters is designed for - 3 db at 5.6 mhz. the filters can be bypassed if external filtering with other characteristics is desired. 7.1.4 t riple 8- bit analog - to - digital conversion three identical adcs are used to convert y, u and v with 16 mhz data rate. a multi-step type adc is applied here. 7.2 digital processing at 1f h level 7.2.1 o verload detection the overload detection provides information to make efficient use of the agc. the number of overflows per video field in the luminance channel is accumulated by a 14-bit counter. the 8 msbs of this counter can be read out by the microprocessor respectively via the i 2 c-bus. overflow levels can be programmed as 216, 224, 232 and 240. 7.2.2 d igital clamp correction for uv during 32 samples within the clamp position the clamp error is measured and accumulated to make a low-pass filtered value of the clamp error. then a vertical recursive filter is used to further low-pass this error value. this value can be read by the microprocessor or directly be used to correct the clamp error. it is also possible to give a fixed correction value by the microprocessor. 7.2.3 4:4:4 to 4:1:1 down - sampling and uv coring the u and v samples from the adc are low-pass filtered, before being subsampled with a factor of 2. coring is applied to the subsampled signal to obtain no gain for low amplitudes which is considered to be noise. coring levels can be programmed as 0 (off), 1 2 , 1 and 2 lsb. the u and v samples from the 4 :2:2 data are low-pass filtered again, before being subsampled a second time with a factor of 2 and formatted to 4 :1:1 format. 7.2.4 y- delay the y samples can be shifted onto 8 positions w.r.t. the uv samples. this shift is meant to account for a possible difference in delay previous to the saa4977h. the zero delay setting is suitable for the nominal case of aligned input data according to the interface format standard. the other settings provide four samples less delay to three sample more delay in y.
1998 jul 23 9 philips semiconductors preliminary speci?cation besic saa4977h 7.2.5 h orizontal compression for displaying 4 : 3 sources on 16 : 9 screens a horizontal signal compression can be done by data interpolation. therefore two horizontal compression factors of either 4 3 or 7 6 are possible. via the i 2 c-bus the compression can be switched on or off and the compression mode 16 : 9 or 14 : 9 can be selected. when the compression mode is active, a reduced number of the interpolated data is stored in the field memory. to achieve sufficiently high accuracy in interpolation variable phase delay filters are used (vpd10 for luminance, a multiplexed vpd06 for uv). 7.3 digital processing at 2f h level 7.3.1 4:1:1 to 4:2:2 up - conversion an up-converter to 4:2:2 is applied with a linear interpolation filter for creation of the extra samples. these are combined with the original samples from the 4 :1:1 stream. 7.3.2 dcti the digital colour transient improvement (dcti) is intended for u and v signals originating from a 4 :1:1 source. horizontal transients are detected and enhanced without overshoots by differentiating, make absolute and again differentiating the u and v signals separately. this results in a 4:4:4 u and v bandwidth. to prevent third harmonic distortion, typical for this processing, a so called over the hill protection prevents peak signals becoming distorted. via the i 2 c-bus it is possible to control: gain width (see fig.4), threshold (i.e. immunity against noise), selection of simple or improved first differentiating filter (see fig.3), limit for pixel shift range (see fig.5), common or separate processing of u and v signals, hill protection mode (i.e. no discolourations in narrow colour gaps), low-pass filtering for u and v signals (see fig.6) and a so called super hill mode, which avoids discolourations in transients within a colour component. 7.3.3 y- peaking a linear peaking is applied, which amplifies the luminance signal in the middle and the upper ranges of the bandwidth. the filtering is an addition of: the original signal the original signal high-passed with maximum gain at frequency = 1 2 f s (8 mhz) the original signal band-passed with centre frequency = 1 4 f s (4 mhz) the original signal band-passed with centre frequency of 2.38 mhz. the band-passed and high-passed signals are weighted with factors 0, 1 16 , 2 16 , 3 16 , 4 16 , 5 16 , 6 16 , and 8 16 , resulting in a maximum gain difference of 2 db at the centre frequencies. coring is added to obtain no gain for low amplitudes in the high-pass and band-pass filtered signal, which is considered to be noise. coring levels can be programmed as 0 (off), 8, 16, 24 to 120 lsb w.r.t. the (signed) 11-bit filtered signal. in addition the peaking gain can be reduced depending on the signal amplitude, programming range 0 (no attenuation), 1 4 , 2 4 , and 4 4 . it is also possible to make larger undershoots than overshoots, programming range 0 (no attenuation of undershoots), 1 4 , 2 4 , and 4 4 . 7.3.4 y- delay the y samples can be shifted onto 8 positions w.r.t. the uv samples. this shift is meant to account for a possible difference in delay previous to the saa4977h. the zero delay setting is suitable for the nominal case of aligned input data. the other settings provide one to seven samples less delay in y. 7.3.5 s idepanels and blanking sidepanels are generated by switching y and the 4 msbs of u and v to certain programmable values. the start and stop values for the sidepanels w.r.t. the rising edge of the hrd signal are programmable in a resolution of 4 lld clock cycles. in addition, a fine shift of 0 to 3 lld clock cycles of both values can be achieved. blanking is done by switching y to value 64 at 10-bit word and uv to value 0 (in 2s complement). blanking is controlled by a composite signal hvbda, consisting of a horizontal part hbda and a vertical part vbda. set and reset value of the horizontal control signal hbda are programmable w.r.t. the rising edge of the hrd signal, set and reset value of the vertical control signal vbda are programmable w.r.t. the rising edge of the va signal. the range of the y output signal can be selected between 9 and 10 bits. in the case of 9 bits for the nominal signal there is room left for undershoot and overshoot (adding up to a total of 10 bits). in the case of selecting all 10 bits of the luminance dac for the nominal signal any under or overshoot will be clipped (see fig.11).
1998 jul 23 10 philips semiconductors preliminary speci?cation besic saa4977h fig.3 dcti first differentiating filter; transfer function with variation of control signal dcti_ddx_sel. (1) dcti_ddx_sel = 1. (2) dcti_ddx_sel = 0. handbook, halfpage 0 0.25 1 0 0.2 mgm689 signal amplitude f/f s 0.4 0.6 0.8 0.05 0.1 0.15 0.2 (2) (1) handbook, full pagewidth mgm690 digital signal amplitude samples (1) (5) (4) (3) (2) 500 - 100 - 200 300 400 - 300 200 - 400 100 0 - 500 fig.4 dcti with variation of gain setting (limit = 1). (1) input signal. (2) gain = 1. (3) gain = 3. (4) gain = 5. (5) gain = 7.
1998 jul 23 11 philips semiconductors preliminary speci?cation besic saa4977h handbook, full pagewidth mgm691 digital signal amplitude samples (1) (4) (3) (2) 500 - 100 - 200 300 400 - 300 200 - 400 100 0 - 500 fig.5 dcti with variation of limit setting (gain = 7). (1) input signal. (2) limit = 1. (3) limit = 2. (4) limit = 3. fig.6 dcti post-filter transfer function. handbook, halfpage 0 0.5 1.2 0 0.4 0.8 mgm692 0.1 0.2 0.3 0.4 signal amplitude f/f s
1998 jul 23 12 philips semiconductors preliminary speci?cation besic saa4977h fig.7 transfer function of the peaking high-pass filter with variation of b ( a =0; t = 0). (1) b = 1 16 . (2) b = 2 16 . (3) b = 3 16 . (4) b = 4 16 . (5) b = 5 16 . (6) b = 6 16 . (7) b = 8 16 . handbook, full pagewidth 0.5 10 0 f/f s signal amplitude (db) 0 0.1 0.2 0.3 0.4 2 4 6 8 mgm594 (7) (6) (5) (4) (3) (2) (1)
1998 jul 23 13 philips semiconductors preliminary speci?cation besic saa4977h fig.8 transfer function of the peaking band-pass with variation of a ( b =0; t = 0). (1) a = 1 16 . (2) a = 2 16 . (3) a = 3 16 . (4) a = 4 16 . (5) a = 5 16 . (6) a = 6 16 . (7) a = 8 16 . handbook, full pagewidth 0.5 10 0 f/f s signal amplitude (db) 0 0.1 0.2 0.3 0.4 2 4 6 8 mgm595 (7) (6) (5) (4) (3) (2) (1)
1998 jul 23 14 philips semiconductors preliminary speci?cation besic saa4977h fig.9 transfer function of peaking low band-pass with variation of t ( a =0; b = 0). (1) t = 1 16 . (2) t = 2 16 . (3) t = 3 16 . (4) t = 4 16 . (5) t = 5 16 . (6) t = 6 16 . (7) t = 8 16 . handbook, full pagewidth 0.5 10 0 f/f s signal amplitude (db) 0 0.1 0.2 0.3 0.4 2 4 6 8 mgm596 (7) (6) (5) (4) (3) (2) (1)
1998 jul 23 15 philips semiconductors preliminary speci?cation besic saa4977h 7.4 digital-to-analog conversion three identical 10-bit dacs are used to map the 4 : 4 : 4 data to analog levels. 7.5 microprocessor the saa4977h contains an embedded 80c51 microprocessor core including a 256 byte ram and 16 kbyte rom. the microprocessor runs on a 16 mhz clock, generated by dividing the 32 mhz display clock by a factor of 2. for controlling internal registers a host interface, consisting of a parallel address and data bus, is built-in, that can be addressed as internal aux ram via movx type of instructions. 7.5.1 i 2 c- bus the i 2 c-bus interface in the saa4977h is used in a slave receive and transmit mode for communication with a central system microprocessor. the standardized bus frequencies of both 100 khz and 400 khz can be dealt with. the i 2 c-bus slave address of the saa4977h is 0110100 r/ w. for a detailed description of the transmission protocol refer to brochure the i 2 c-bus and how to use it (order number 9398 393 40011) and to application note i 2 c-bus register specification of the saa4977h (an98054). 7.5.2 snert- bus a snert interface is built-in, which operates in a master receive and transmit mode for communication with peripheral circuits such as the saa4990h or saa4991wp. the snert interface replaces the standard uart interface. in contrast to the 80c51 uart interface there are additional special function registers and there is no byte separation time between address and data. the snert interface transforms the parallel data from the microprocessor into 1 mbaud snert data. the snert-bus consists of three signals: sncl used as the serial clock signal and is generated by the snert interface; snda used as the bidirectional data line, and snrst used as the reset signal and is generated by the microprocessor to indicate the start of a transmission. the read or write operation must be set by the microprocessor. when writing to the bus, 2 bytes are loaded by the microprocessor: one for the address, the other for the data. when reading from the bus, one byte is loaded by the microprocessor for the address, the received byte is the data from the addressed snert location. 7.5.3 i/o ports a parallel 8-bit i/o port (p1) is available, where p1.0 is used as the snert reset signal (snrst), p1.1 to p1.5 can be used for application specific control signals, and p1.6 and p1.7 are used as i 2 c-bus signals (scl and sda). 7.5.4 w atchdog t imer the microprocessor contains an internal watchdog timer, which can be activated by setting the bit 4 in sfr pcon. only a synchronous reset will clear this bit. to prevent a system reset the watchdog timer must be reloaded in time. the watchdog timer is incremented every 0.75 ms. the time interval between the timers reloading and the occurrence of a reset depends on the reloaded 8-bit value. 7.6 memory controller the memory controller provides all necessary acquisition clock related write signals (we and rstw) and display clock related read signals (re and ie2) to control one or two-field memory concepts. furthermore the drive signals (hdfl and vdfl) for the horizontal and vertical deflection power stages are generated. also a horizontal blanking pulse blnd is generated which can be used for peripheral circuits as saa4990h. the memory controller is connected to the microprocessor via the host interface. start and stop values for all pulses, referring to the corresponding horizontal or vertical reference signal, are programmable under control of the internal software. to allow user access to these control signals via the i 2 c-bus a range of subaddresses is reserved; for a detailed description of this user interface refer to application note i 2 c-bus register specification of the saa4977h (an98054). 7.6.1 we the write enable signal for field memory 1 is a composite signal consisting of a horizontal and a vertical part. the horizontal position w.r.t the rising edge of the ha signal and the vertical position w.r.t the rising edge of the va signal are programmable.
1998 jul 23 16 philips semiconductors preliminary speci?cation besic saa4977h 7.6.2 rstw reset write signal for field memory 1; this signal is derived from the positive edge of the va input signal and has a pulse width of 64 m s. 7.6.3 re the read enable signal for field memory 1 is a composite signal consisting of a horizontal and a vertical part. the horizontal position w.r.t the rising edge of the ha signal and the vertical position w.r.t the rising edge of the va signal are programmable. 7.6.4 ie2 input enable signal for field memory 2, can be directly set or reset by the microprocessor. 7.6.5 hdfl horizontal deflection signal for driving a deflection circuit; this signal has a cycle time of 32 m s and a pulse width of 76 lld clock cycles. 7.6.6 vdfl vertical deflection signal for driving a deflection circuit; this signal has a cycle time of 10 ms; the start and stop value w.r.t the rising edge of the va signal is programmable in steps of 16 m s. 7.6.7 blnd horizontal blanking signal for peripheral circuits e.g. saa4990h, start and stop values w.r.t. the rising edge of hrd are programmable. 7.7 line locked clock generation 7.7.1 p hase comparison of ha rising edge with generated h ref signal the ha signal, which has a nominal period of 64 m s, is used as a timing reference for the line locked acquisition clock system. this ha signal may vary in position from application to application, related to the active video part. the phase comparator measures the delay between the ha and the internally generated, clock synchronous h ref signal. 7.7.2 pll clock generator running at 32 mh z (2048 clock cycles per line ) the basic frequency of the clock generator is 32 mhz. the type of pll is known as petra pll. this is a purely analog clock generator, with analog frequency control via a loop filter on the measured phase error. 7.7.3 d ivide - by -2 for master clock 16 mh z a simple clock divider is used to generate 16 mhz out of 32 mhz. the advantage of this construction is the inherent 50% duty cycle on the acquisition clock. 7.7.4 d ivide by another 1024 to generate line frequent , clock synchronous h ref signal the video lines contain 1024 clock cycles of 16 mhz. therefore, frequency division by 1024 creates a 50% duty cycle line frequent signal h ref . 7.8 clock and sync interfacing typically the circuit operates as a two clock system, i.e. lla is supplied with a 16 mhz clock and lld with a 32 mhz clock. the line locked display clock lld must be provided by the application. also a line frequent signal must be provided by the application at pin ha. a vertical 50 or 60 hz synchronization signal has to be applied on pin va. it is also possible to use an external line locked acquisition clock, which must be provided at pin lla. this operation mode can be selected by the selclk pin. when using the external acquisition clock the ha signal must be synchronous to the acquisition clock. a display clock synchronous line frequent signal is put out at pin hrd providing a duty factor of 50%. the rising edge of hrd is also the reference for display related control signals as blnd, re, hdav and hbda. the acquisition clock is buffered internally and put out as serial write clock (swc) for supplying the field memory.
1998 jul 23 17 philips semiconductors preliminary speci?cation besic saa4977h 7.9 4:1:1 i/o interfacing table 2 digital input and output bus format the first phase of the 4:1:1 yuv dataword is available on the output bus one swc clock cycle after the rising edge of the we signal. the start position, when the first phase of the 4:1:1 yuv data word is expected on the input bus, can be defined by the internal control signal hdav. the luminance output signal is in 8-bit straight binary format, whereas u and v input signals are in 2s complement format. also the luminance input signal is expected in 8-bit straight binary format, whereas u and v input signals are expected in 2s complement format. the u and v input signals are inverted if the corresponding control bit uv_inv is set via the i 2 c-bus. 7.10 test mode operation the saa4977h provides a test mode function which should not be entered by the customer. if the trst input is driven high, different test modes can be selected by applying a high to the tms input for a defined number of lld clock cycles. to exit the test mode tms and trst must be driven low. output pin 4:1:1 format input pin yo7 y07 y17 y27 y37 yi7 yo6 y06 y16 y26 y36 yi6 yo5 y05 y15 y25 y35 yi5 yo4 y04 y14 y24 y34 yi4 yo3 y03 y13 y23 y33 yi3 yo2 y02 y12 y22 y32 yi2 y01 y01 y11 y21 y31 yi1 yo0 y00 y10 y20 y30 yi0 uvo7 u07 u05 u03 u01 uvi7 uvo6 u06 u04 u02 u00 uvi6 uvo5 v07 v05 v03 v01 uvi5 uvo4 v06 v04 v02 v00 uvi4
1998 jul 23 18 philips semiconductors preliminary speci?cation besic saa4977h 7.11 i 2 c-bus control registers address bit name description subaddress 00h to 2fh: reserved; note 1 subaddress 30h to 32h (agc) 30h 0 to 7 agc_y agc gain for y channel (2s complement relative to 0 db): upper 8 bits 31h 0 to 7 agc_uv agc gain for u and v channel (2s complement relative to 0 db): upper 8 bits 32h 0 agc_y agc gain for y channel lsb 1 agc_uv agc gain for uv channel lsb 2 standby_f front-end in standby mode if high 3 aaf_bypass bypass for pre?lter if high 4to7 - reserved subaddress 33h (uv clamp correction) 33h 0 and 1 uvclcor_mode clamp correction mode = auto, ?xed, keep, reserved 2 to 4 uclcor_fval ?xed value for clamp correction u channel 5 to 7 vclcor_fval ?xed value for clamp correction v channel subaddress 34h (uv coring) 34h 0 and 1 uvcoring coring level = 0, 0.5, 1 and 2 lsb 2 and 3 - reserved 4 and 5 uvcl_tau vertical ?ltering of measured clamp 6 and 7 - reserved subaddress 35h (y delay) 35h 0 to 2 ydelay_f variable y-delay in lla clock cycles: - 4, - 3, - 2, - 1, 0, 1, 2 and 3 3 and 4 overl_thr overload threshold: (216, 224, 232, 240) 5 ?ll_mem ?ll memory with constant value if high 6 and 7 - reserved subaddress 36h and 37h (dcti) 36h 0 to 2 dcti_gain dcti gain: 0, 1, 2, 3, 4, 5, 6 and 7 3 to 6 dcti_threshold dcti threshold: 0, 1 to 15 7 dcti_ddx_sel dcti selection of ?rst differentiating ?lter; see fig.3 37h 0 and 1 dcti_limit dcti limit for pixel shift range: 0, 1, 2 and 3 2 dcti_separate dcti separate processing of u and v signals; 0 = off, 1 = on 3 dcti_protection dcti over the hill protection; 0 = off, 1 = on 4 dcti_?lteron dcti post-?lter; 0 = off, 1 = on 5 dcti_superhill dcti super hill mode; 0 = off, 1 = on 6 and 7 - reserved subaddress 38h and 3ah (peaking) 38h 0 to 2 pk_alpha peaking alpha: 1 16 (0, 1, 2, 3, 4, 5, 6, 8) 3 to 5 pk_beta peaking beta: 1 16 (0, 1, 2, 3, 4, 5, 6, 8) 6 and 7 - reserved
1998 jul 23 19 philips semiconductors preliminary speci?cation besic saa4977h note 1. detailed information about the software dependent i 2 c-bus registers can be found in application note i 2 c-bus register specification of the saa4977h (an98054). 8 limiting values in accordance with the absolute maximum rating system (iec 134). 9 thermal characteristics 39h 0 to 2 pk_tau peaking tau: 1 16 (0, 1, 2, 3, 4, 5, 6, 8) 3 and 4 pk_delta peaking amplitude dependent attenuation: 1 4 (0, 1, 2, 4) 5 and 6 pk_neggain peaking attenuation of undershoots: 1 4 (0, 1, 2, 4) 7 - reserved 3ah 0 to 3 pk_corthr peaking coring threshold 0, 8, 16 to 120 lsb 4to7 - reserved subaddress 3bh and 3ch (sidepanels overlay) 3bh 0 to 3 overlay_u sidepanels overlay u (4 msb) 4 to 7 overlay_v sidepanels overlay v (4 msb) 3ch 0 to 7 overlay_y sidepanels overlay y (8 msb) subaddress 3dh to 3fh (sidepanel position) 3dh 0 to 7 sidepanel_start sidepanel start position (8 msb) w.r.t. the rising edge of hrd signal 3eh 0 to 7 sidepanel_stop sidepanel stop position (8 msb) w.r.t. the rising edge of hrd signal 3fh 0 and 1 sidepanel_fdel ?ne delay of sidepanel signal in lld clock cycles: 0, 1, 2 and 3 2 output_range output range (output range = 0: 9 bit for the nominal output signal, black level: 288 and white level: 767; output range = 1: 10 bit for the nominal output signal, black level 64 and white level 1023) 3 uv_inv inverts uv input signals: 0 = no inversion, 1 = inversion 4 to 6 ydelay_out variable y-delay in lld clock cycles: - 7, - 6, - 5, - 4, - 3, - 2, - 1 and 0 7 - reserved symbol parameter min. max. unit v dda(1,2,3) analog supply voltage front-end - 0.5 +5.25 v v ddd(1,2,3) digital supply voltage front-end - 0.5 +5.25 v v dda(4,5) analog supply voltage back-end - 0.5 +3.45 v v ddd(4,5,6) digital supply voltage back-end - 0.5 +3.45 v v ddio digital i/o supply voltage back-end - 0.5 +5.25 v v i input voltage for all i/o pins - 0.5 +5.25 v t stg storage temperature - 20 +150 c t amb operating ambient temperature - 20 +60 c symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient in free air 50 k/w address bit name description
1998 jul 23 20 philips semiconductors preliminary speci?cation besic saa4977h 10 characteristics v ddd(1,2,3) = 4.75 to 5.25 v; v dda(1,2,3) = 4.75 to 5.25 v; v ddd(4,5,6) = 3.15 to 3.45 v; v dda(4,5) = 3.15 to 3.45 v; t amb = 0 to 60 c; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supply v dda(1,2,3) analog supply voltage front-end 4.75 5.0 5.25 v v ddd(1,2,3) digital supply voltage front-end 4.75 5.0 5.25 v i dda(1,2,3) analog supply current front-end - 85 100 ma i ddd(1,2,3) digital supply current front-end - 65 80 ma v dda(4,5) analog supply voltage back-end 3.15 3.3 3.45 v v ddd(4,5,6) digital supply voltage back-end 3.15 3.3 3.45 v v ddio i/o supply voltage back-end 4.75 5.0 5.25 v i dda(4,5) analog supply current back-end - 25 35 ma i ddd(4,5,6) digital supply current back-end - 40 55 ma i ddio i/o supply current back-end - 110 ma dissipation p tot total power dissipation -- 1.3 w luminance input signal (y clamp level digital 16) v i(p-p) y input level (peak-to-peak value) agc ?xed at 0 db; note 1 0.95 1.00 1.05 v c i input capacitance - 715 pf i li input leakage current clamp not active -- 100 na i i input current during clamping -- 150 m a a agc(max) maximum agc attenuation 5.75 6 - db g agc(max) maximum agc gain 5.75 6 - db a agc(acc) agc attenuation accuracy digital - 8 - bits g agc(acc) agc gain accuracy digital - 8 - bits colour difference input signals (u and v clamp level digital 128) v i(p-p) u input level (peak-to-peak value) agc ?xed at 0 db; note 1 1.29 1.34 1.39 v v input level (peak-to-peak value) agc ?xed at 0 db; note 1 1.00 1.05 1.10 v c i input capacitance -- 15 pf i li input leakage current clamp not active -- 100 na i i input current during clamping -- 150 m a a agc(max) maximum agc attenuation 5.75 6 - db g agc(max) maximum agc gain 5.75 6 - db a agc(acc) agc attenuation accuracy digital - 8 - bits g agc(acc) agc gain accuracy digital - 8 - bits
1998 jul 23 21 philips semiconductors preliminary speci?cation besic saa4977h analog input transfer function (sample rate 16 mhz/8 bits) f clk maximum sample clock 18 -- mhz inl integral non linearity ramp input signal - 1 - +1 lsb dnl differential non linearity ramp input signal - 0.75 - +0.75 lsb s/n signal-to-noise ratio nominal amplitude; 0 to 8 mhz 43 -- db hd harmonic distortion (2nd to 5th harmonic) 95% amplitude; y at 4.3 mhz; uv at 1 mhz -- 50 - 37 db g dif differential gain f clk = 4.4 mhz; adc only; at nominal agc setting - 12 % svr supply voltage rejection note 2 34 -- db analog y, u and v input ?lter (third order linear phase ?lter with notch at f clk ) f ( - 3db) 3 db down frequency f clk = 16 mhz 5.4 5.6 5.8 mhz a (0.5) attenuation at 1 2 f clk (8 mhz) 7 8 - db a sb stop band attenuation 30 -- db f notch notch frequency 15.5 16 16.5 mhz t d(g) group delay f clk = 4 mhz - 55 65 ns t d(g)(dif) differential group delay within 1 to 6 mhz - 20 30 ns luminance output signal (output_range = 0: y black level digital 288, white level digital 767, output_range = 1: y black level digital 64, white level digital 1023); see fig.11 v o(p-p) y output level (peak-to-peak value) z l =2k w 1.28 1.34 1.40 v r o output resistance - 50 100 w r l resistive load 1 2 - k w c l capacitive load -- 25 pf svr supply voltage rejection note 2 34 -- db a ct crosstalk attenuation between outputs 0 to 10 mhz 40 -- db s/n signal-to-noise ratio nominal amplitude; 0to10mhz 46 -- db colour difference output signals (u and v digital range 0 to 1023) v o(p-p) u output level (peak-to-peak value) z l =2k w 1.28 1.34 1.40 v v output level (peak-to-peak value) z l =2k w 1.28 1.34 1.40 v g m(u-v) gain matching u to v - 13 % r o output resistance - 50 100 w r l resistive load 1 2 - k w c l capacitive load -- 25 pf svr supply voltage rejection note 2 34 -- db symbol parameter conditions min. typ. max. unit
1998 jul 23 22 philips semiconductors preliminary speci?cation besic saa4977h a ct crosstalk attenuation between outputs 0 to 10 mhz 40 -- db s/n signal-to-noise ratio nominal amplitude; 0to10mhz 46 -- db output transfer function (sample rate 32 mhz/10 bits) inl integral non linearity - 2 - +2 lsb dnl differential non linearity - 1 - +1 lsb digital output signals: yo, uvo, we and rstw (c l = 15 pf); timing referred to swc clock v oh high-level output voltage i oh = - 2.0 ma 2.4 -- v v ol low-level output voltage i ol = 1.6 ma -- 0.4 v t d(o) output delay time see fig.10 -- 20 ns t h(o) output hold time see fig.10 4 -- ns digital output signal: swc (c l = 15 pf); timing referred to lla clock v oh high-level output voltage i oh = - 2.0 ma 2.4 -- v v ol low-level output voltage i ol = 1.6 ma -- 0.4 v t d(o) output delay time see fig.10 3 - 12 ns digital output signal: hrd v oh high-level output voltage i oh = - 2.0 ma 2.4 -- v v ol low-level output voltage i ol = 1.6 ma -- 0.4 v digital output signals: ie2, blnd, re, hdfl and vdfl (c l = 15 pf); timing referred to lld clock v oh high-level output voltage i oh = - 2.0 ma 2.4 -- v v ol low-level output voltage i ol = 1.6 ma -- 0.4 v t d(o) output delay time see fig.10 -- 20 ns t h(o) output hold time see fig.10 4 -- ns digital input/output signals: p1.1 to p1.5 and snrst v oh high-level output voltage i oh = - 0.06 ma 2.4 -- v v ol low-level output voltage i ol = 1.6 ma 0 - 0.4 v v ih high-level input voltage 2.0 - 5.5 v v il low-level input voltage 0 - 0.8 v digital input signals: yi and uvi; timing referred to lld clock v ih high-level input voltage 2.0 - 5.5 v v il low-level input voltage -- 0.8 v t su(i) input set-up time see fig.10 4 -- ns t h(i) input hold time see fig.10 3 -- ns symbol parameter conditions min. typ. max. unit
1998 jul 23 23 philips semiconductors preliminary speci?cation besic saa4977h digital input signal: ha; timing referred to lla clock (only when selclk = 0, ha used as digital horizontal reference) v ih high-level input voltage 2.0 - 5.5 v v il low-level input voltage -- 0.8 v t su(i) input set-up time see fig.10 7 -- ns t h(i) input hold time see fig.10 4 -- ns digital input signals: trst, tms, rst and va v ih high-level input voltage 2.0 - 5.5 v v il low-level input voltage -- 0.8 v digital input clock signal: lla f lla sample clock frequency 14 16 34 mhz d clk clock duty factor 40 50 60 % v ih high-level input voltage 2.4 -- v v il low-level input voltage -- 0.6 v t r clock rise time see fig.10 -- 5ns t f clock fall time see fig.10 -- 5ns digital input clock signal: lld f lld sample clock frequency 30 32 34 mhz d clk clock duty factor 40 50 60 % v ih high-level input voltage 2.4 -- v v il low-level input voltage -- 0.6 v t r clock rise time see fig.10 -- 5ns t f clock fall time see fig.10 -- 5ns i 2 c-bus signal: sda and scl; note 3 v ih high-level input voltage 0.7v ddio -- v v il low-level input voltage -- 0.3v ddio v v ol low-level output voltage i ol = 3.0 ma -- 0.4 v f scl scl clock frequency -- 400 khz t hd;sta hold time start condition 0.6 -- m s t low scl low time 1.3 -- m s t high scl high time 0.6 -- m s t su;dat data set-up time 100 -- ns t su;dat1 data set-up time (before repeated start condition) 0.6 -- m s t su;dat2 data set-up time (before stop condition) 0.6 -- m s t su;sta set-up time repeated start 0.6 -- m s t su;sto set-up time stop condition 0.6 -- m s symbol parameter conditions min. typ. max. unit
1998 jul 23 24 philips semiconductors preliminary speci?cation besic saa4977h notes 1. with agc at - 3 db, u full adc range is obtained at v i = 1.89 v; with agc at +6 db, u full adc range is obtained at v i = 0.67 v; with agc at - 3 db, v full adc range is obtained at v i = 1.48 v; with agc at +6 db, v full adc range is obtained at v i = 0.52 v. 2. supply voltage ripple rejection, measured over a frequency range from 20 hz to 50 khz. this includes 1 2 f v , f v , 2f v , f h and 2f h which are major load frequencies: svr is relative variation of the full scale analog input for a supply variation of 0.25 v. 3. the ac characteristics are in accordance with the i 2 c-bus specification for fast mode (clock frequency maximum 400 khz). information about the i 2 c-bus can be found in the brochure i 2 c-bus and how to use it (order number 9398 393 40011). 4. more information about the snert-bus protocol can be found in application note the snert-bus specification (an95127). snert-bus: snda and sncl; note 4 v oh high-level output voltage i oh = - 2.0 ma 2.4 -- v v ol low-level output voltage i ol = 1.6 ma -- 0.4 v v ih high-level input voltage 2.0 - 5.5 v v il low-level input voltage -- 0.8 v t su(i) input set-up time 700 -- ns t h(i) input hold time 0 -- ns t cycle sncl cycle time - 1 -m s t h(o) output hold time 50 -- ns symbol parameter conditions min. typ. max. unit fig.10 timing diagram. handbook, full pagewidth mgm597 clock 2.4 v 1.5 v 0.6 v 2.0 v 0.8 v 2.4 v 0.4 v input data output data t h(o) t d(o) t r t f t su(i) t h(i)
1998 jul 23 25 philips semiconductors preliminary speci?cation besic saa4977h 11 application the saa4977h supports two different up-converter concepts. the simple one is shown in fig.12. in this application only one field memory saa4955tj is needed for a 100 hz conversion based on a field repetition algorithm (aabb mode). the concept can be upgraded by a noise reduction based on a motion adaptive field recursive filter if the saa4956tj is used instead of the saa4955tj. the saa4977h supports a dual-clock system. the acquisition clock is taken from the digital front-end. the display control is based on a clock generated by an external h-pll. by this structure the stability of the display is enhanced compared to a one-clock system if an unstable source like a vcr is used as an input. the second system supported by the saa4977h is shown in fig.13. this concept needs two field memories (saa4955tj) and the signal processing ic melzonic (saa4991wp). the saa4991wp allows a vector based motion estimation and compensation for a display of 100 hz pictures in high-end tv sets which is free of motion artefacts. it additionally provides a variable vertical zoom function, noise and cross colour reduction. furthermore a multi-pip feature is supported making use of the field memories. fig.11 luminance levels. handbook, full pagewidth 1.00 v black 16 white 255 input 8 bit output 10 bit output_range = 1 output_range = 0 00 64 1023 1023 0 256 288 767 1.34 v mgm598
1998 jul 23 26 philips semiconductors preliminary speci?cation besic saa4977h fig.12 application diagram 1. (1) alternatively saa4956tj. handbook, full pagewidth mgm599 display pll saa4955tj (1) saa4977h uin yin vin 19, 22 +3.3 v 20, 21, 23 +5 v 8, 11, 69, 75, 80 +3.3 v 17, 18, 19, 23, 25, 29, 46, 67 14 to 16, 21, 27, 31, 48 to 50, 33, 65, 73, 77, 78 n.c. 3 to 7, 10, 12, 13, 64, 66 1, 2, 39, 40 +5 v 45 9 3 44 4 43 5 42 6 41 7 40 8 39 9 38 10 37 11 36 12 35 13 34 79 76 74 1 2 71 72 yout uout vout sda scl src hdfl vdfl 70 15 16 17, 18 38 37 36 35 34 33 32 31 30 29 28 27 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 ha va d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 24 14 24 47 32 28 26 30 51 52 53 54 55 56 57 58 59 60 61 25 62 26 63 rstw swc we hrd re 20 22 68 10 m f 8.2 k w
1998 jul 23 27 philips semiconductors preliminary speci?cation besic saa4977h fig.13 application diagram 2. handbook, full pagewidth mgm600 display pll saa4991wp saa4977h yin uin vin 1, 2, 39, 40 2, 3, 5, 6, 7, 22, 26, 27, 47, 60, 63, 79 to 84 1, 4, 20, 42, 46, 65, 78 +5 v 8, 11, 69, 75, 80 +3.3 v 17, 18, 19, 23, 25, 29, 46, 67 14 to 16, 21, 27, 31, 48 to 50, 33, 65, 73, 77, 78 n.c. n.c. 3 to 7, 10, 64, 66 +5 v 45 9 44 43 41 42 40 41 38 40 37 39 36 38 35 37 34 36 35 34 79 76 74 1 2 71 72 yout uout vout sda scl src hdfl vdfl 70 48 49 50 51 52 53 54 55 56 57 58 59 ha va d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 61 24 47 32 28 26 30 51 52 53 54 55 56 57 58 59 60 61 62 63 rstw swc we hrd re 44 43 8 to 10 12 13 sncl snda saa4955tj fm1 19, 22 +3.3 v 20, 21, 23 +5 v 3 4 5 6 7 8 9 10 11 12 13 15 16 17, 18 38 37 36 35 34 33 32 31 30 29 28 27 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 24 14 25 26 re1 we2 1, 2, 39, 40 64 66 67 68 69 70 71 72 73 74 76 33 32 31 30 28 29 11 75 77 saa4955tj fm2 19, 22 62 45 +3.3 v 20, 21, 23 +5 v 3 4 5 6 7 8 9 10 11 12 13 15 16 17, 18 38 37 36 35 34 33 32 31 30 29 28 27 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 24 25 24 23 21 19 18 17 16 15 14 13 12 14 25 26 re2 20 22 68 10 m f 8.2 k w
1998 jul 23 28 philips semiconductors preliminary speci?cation besic saa4977h 12 package outline unit a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 0.25 0.05 2.90 2.65 0.25 0.45 0.30 0.25 0.14 14.1 13.9 0.8 1.95 18.2 17.6 1.2 0.8 7 0 o o 0.2 0.2 0.1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 1.0 0.6 sot318-2 d (1) (1) (1) 20.1 19.9 h d 24.2 23.6 e z 1.0 0.6 d b p e q e a 1 a l p detail x l (a ) 3 b 24 c b p e h a 2 d z d a z e e v m a 1 80 65 64 41 40 25 pin 1 index x y d h v m b w m w m 95-02-04 97-08-01 0 5 10 mm scale qfp80: plastic quad flat package; 80 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm sot318-2 a max. 3.2
1998 jul 23 29 philips semiconductors preliminary speci?cation besic saa4977h 13 soldering 13.1 introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (order code 9398 652 90011). 13.2 re?ow soldering reflow soldering techniques are suitable for all qfp packages. the choice of heating method may be influenced by larger plastic qfp packages (44 leads, or more). if infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 50 and 300 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. 13.3 wave soldering wave soldering is not recommended for qfp packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. caution wave soldering is not applicable for all qfp packages with a pitch (e) equal or less than 0.5 mm. if wave soldering cannot be avoided, for qfp packages with a pitch (e) larger than 0.5 mm, the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 13.4 repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1998 jul 23 30 philips semiconductors preliminary speci?cation besic saa4977h 14 definitions 15 life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. 16 purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
1998 jul 23 31 philips semiconductors preliminary speci?cation besic saa4977h notes
internet: http://www.semiconductors.philips.com philips semiconductors C a worldwide company ? philips electronics n.v. 1998 sca60 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reli able and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. middle east: see italy netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 pakistan: see singapore philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 319762, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: al. vicente pinzon, 173, 6th floor, 04547-130 s?o paulo, sp, brazil, tel. +55 11 821 2333, fax. +55 11 821 2382 spain: balmes 22, 08007 barcelona, tel. +34 93 301 6312, fax. +34 93 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 5985 2000, fax. +46 8 5985 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2741 fax. +41 1 488 3263 taiwan: philips semiconductors, 6f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2865, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. +90 212 279 2770, fax. +90 212 282 6707 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 181 730 5000, fax. +44 181 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 625 344, fax.+381 11 635 777 for all other countries apply to: philips semiconductors, international marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 34 waterloo road, north ryde, nsw 2113, tel. +61 2 9805 4455, fax. +61 2 9805 4466 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 160 1010, fax. +43 160 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 200 733, fax. +375 172 200 773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 689 211, fax. +359 2 689 102 canada: philips semiconductors/components, tel. +1 800 234 7381 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. +45 32 88 2636, fax. +45 31 57 0044 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615800, fax. +358 9 61580920 france: 51 rue carnot, bp317, 92156 suresnes cedex, tel. +33 1 40 99 6161, fax. +33 1 40 99 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 23 53 60, fax. +49 40 23 536 300 greece: no. 15, 25th march street, gr 17778 tavros/athens, tel. +30 1 4894 339/239, fax. +30 1 4814 240 hungary: see austria india: philips india ltd, band box building, 2nd floor, 254-d, dr. annie besant road, worli, mumbai 400 025, tel. +91 22 493 8541, fax. +91 22 493 0966 indonesia: pt philips development corporation, semiconductors division, gedung philips, jl. buncit raya kav.99-100, jakarta 12510, tel. +62 21 794 0040 ext. 2501, fax. +62 21 794 0080 ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, piazza iv novembre 3, 20124 milano, tel. +39 2 6752 2531, fax. +39 2 6752 2557 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108-8507, tel. +81 3 3740 5130, fax. +81 3 3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381 printed in the netherlands 545104/00/01/pp32 date of release: 1998 jul 23 document order number: 9397 750 03258

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